1. Field of the Invention
The present invention relates to integrated circuit chips and, in particular, to power supply voltage analysis during the designing of such integrated circuit chips.
2. Description of Related Art
A current technological trend in semiconductor design, especially for application specific integrated circuits (ASICs) and other advanced types of chips, is to reduce operating power. This trend drives the power supply voltages and, in turn, the device threshold voltages to lower levels. As the device threshold voltage Vt and the power supply voltage Vdd are reduced, the ratios of noise voltages to Vt and Vdd increase because the noise levels do not scale down at the same rate as Vt and Vdd. Consequently, circuit sensitivity to noise is increased.
Modern technology trends also drive new designs to deliver higher levels of performance, most commonly achieved by increasing signal current levels and/or duty cycles. This further exacerbates the noise problem because the high current levels create local and often sizable resistive voltage drops in the power supply wiring. As a consequence, the full Vdd supply voltage may not be available to power some of the circuits on the chip.
Designers typically address supply noise problems in indirect ways. In some cases, the chip circuitry is painstakingly designed to be more functionally tolerant of a power-supply decrease, also referred to as a power supply collapse. Alternatively, the power distribution can be designed more conservatively, for example, with wider, thicker, or more abundant wiring, to limit the levels of local on-chip current densities. Both approaches apply heuristic and expensive over-design, often sacrificing performance, power consumption, chip area, and/or cost. Moreover, problems related to noise sensitivity are commonly not detected until very late in the design cycle or, worse, after the chip has already been fabricated. Subsequent solutions rely on expensive and time-consuming remodeling and simulation and/or redesign activity.
A few early-stage design strategies aimed at addressing some aspects of the noise problem have been outlined in the academic literature. The article by Stanisic et al., xe2x80x9cPower Distribution Synthesis for Analog and Mixed-Signal ASICs in RAILxe2x80x9d, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 17.4.1-17.4.5, 1993, describes techniques to synthesize an xe2x80x9coptimalxe2x80x9d power distribution network (i.e., determine the power grid topology, interconnect wirewidths, etc.) according to the electrical requirements of fixed, pre-placed circuit objects. This method uses an optimization technique based on simulated annealing, which analyzes iterated random assignments of power-net segment widths, and seeks to converge to an optimum topology using metrics based on the electrical response of the network to the modeled behavior of the circuit objects. In contrast, the article by Mitra et al., xe2x80x9cSubstrate-Aware Mixed-Signal Macrocell Placement in WRIGHTxe2x80x9d, IEEE Journal of Solid-State Circuits, vol. 30, no. 3, pp. 269-278, March 1995, seeks an optimum placement of circuit objects in the context of substrate noise, a phenomenon that most commonly occurs when fast digital circuitry induces variations in the chip substrate voltage which can adversely affect the performance of sensitive analog circuits on the same chip. This work relies on a simulated-annealing-based optimization loop, which iteratively generates an electrical model of the chip substrate and quantitatively assesses the level of the digital/analog interactions for successive placement configurations until some pre-specified metric is satisfied.
One approach to the power distribution problem might involve devising a technique to quickly assess the effects of voltage collapse everywhere in the power grid for any candidate circuit placement. In practice, this has proven difficultxe2x80x94the quantities of placed circuit objects (tens of thousands or more) and the size of the full-chip power distribution are enormous. The first approach described above (i.e., that of Stanisic et al.) targets a small portion of the power distribution, and considers only a handful of circuit objects, specifically, xe2x80x9ctens of blocksxe2x80x9d. The second approach (by Mitra et al.) uses a coarse model of the chip substrate and does not consider the topology of the power distribution at all. The quantity of cell objects is also limited (less than one hundred in the described examples). Neither approach is applicable to a detailed full-chip optimization process. At each and every step, the computation-time complexity scales superlinearly with both the number of circuit objects and the number of circuit nodes in the network model. Moreover, for realistic designs, it would not be unreasonable to require thousands of model updates and corresponding solutions before obtaining an acceptable result. Clearly, any method which limits the analysis complexity at each step of the iterated process would prove useful for analyzing power-grid problems during chip design.
The inventors have determined that consideration of circuit noise sensitivity and power supply voltage drop during chip physical design would be very beneficial in designing and fabricating efficient and reliable integrated circuit chips.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved method of designing integrated circuits.
It is another object of the present invention to provide an improved method of power supply voltage analysis during the designing of integrated circuit chips.
A further object of the invention is to provide a power supply voltage analysis method for use during early stages of designing of such integrated circuit chips.
It is yet another object of the present invention to provide a power supply voltage analysis method which evaluates noise sensitivity of such integrated circuit chips.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of designing an integrated circuit within a power grid comprising initially characterizing circuits in a circuit library for supply currents and voltage ranges and constructing a power grid model based on general power requirements of the integrated circuit under design. The method then includes calculating an impedance matrix representing impedance between ports in the power grid model, assigning selected circuits from the library to the ports, calculating current and voltage at each of the ports, using a cost function to calculate the cost of placement of the assigned circuits, and perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements.
The current at each of the ports may be calculated by summing current requirements of all of the circuits located in the region of the port, and the voltage at each of the ports may be calculated by solving a reduced, pre-factorized set of linear equations that describe the power-grid impedance, supply voltage sources, and port current sources.
Preferably, each circuit in the object library is characterized to determine its average DC supply current requirement and power-supply voltage range for which it functions acceptably. There may be further included, for each circuit in the object library, tabulated current values which depend on relative placement and load to approximate the supply current dependence on output capacitance.
The power grid model represents circuit ports defined by intersection of the power grid model and the physical power grid of an integrated circuit, and preferably the power grid model has a periodicity of a multiple of the periodicity of the physical power grid of the integrated circuit.
After calculating the impedance matrix, the method may further include assigning regions of the power grid to each of the ports. After calculating current and voltage at each node, the method may further include imposing a penalty to each node having a node voltage outside of a predetermined range.
In another aspect, the present invention provides a method of analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design. The method initially comprises providing a library of circuits for use in designing an integrated circuit chip and determining a supply current requirement and an operating voltage range for each circuit in the circuit library. The method then includes calculating an admittance matrix representing the power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid, assigning regions of the power grid to each of the ports, and placing a set of circuits from the circuit library in regions on the power grid. The method further includes calculating a total node current at each of the ports by summing current requirements of all of the circuits located in the regions, calculating a node voltage at each of the ports by solving a pre-factorized matrix representation of a system of linear equations corresponding to the calculated admittance matrix, imposing a penalty to each node having a node voltage outside of a predetermined range, and writing the node voltages and the penalties to a cost-based floorplanning/placement analysis tool.
After writing the node voltages and the penalties to a cost-based floorplanning/placement analysis tool, the method may further include using a cost function to calculate the cost of placement of the assigned circuits, and perturbing the placement of the circuits, if the cost of such placement does not meet design requirements.
Preferably, the method includes calculation of a passive, reduced power grid conductance matrix, Gxe2x80x2, representing a major constituent of the admittance matrix and an electrically identical representation of all power grid resistive elements. The conductance matrix, Gxe2x80x2 may be calculated as follows:       G    ·    v    =      i    ⁢          
        [                                        G            pp                                                G            pi                                                            G            ip                                                G            ii                                ]  xe2x80x83Gxe2x80x2xc2x7xcexdp=ip 
Gxe2x80x2=Gppxe2x88x92(Gpixc2x7Giixe2x88x921xc2x7Gip) 
where G represents the non-reduced admittance representation of the power grid resistor network; v represents the vector of all node voltages in the non-reduced power grid resistor network; i represents the branch currents through all resistors in the non-reduced power grid resistor network;   "AutoLeftMatch"      [                                        G            pp                                                G            pi                                                            G            ip                                                G            ii                                ]  
represents a specific node-ordered variant of G;
Gpp is the admittance representation of power-grid resistors connecting two port nodes; Gip and Gpi are the admittance representations of power-grid resistors connecting port- and internal nodes; Gii is the admittance representation of power-grid resistors connecting two internal nodes; vp is the vector of power-grid port node voltages; vi is the vector of power-grid internal node voltages; ip is the vector of current sources attached to power-grid port nodes. A xe2x80x98portxe2x80x99 node is defined as a network node that is electrically connected to a voltage or current source. All other nodes are xe2x80x98internalxe2x80x99 nodes.
In a further aspect, the present invention provides a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for designing an integrated circuit within a power grid using a library of circuits. The method steps comprise characterizing circuits in the library for supply currents and voltage ranges, constructing a power grid model based on general power requirements of the integrated circuit under design, calculating an impedance matrix representing impedance between ports in the power grid model, assigning selected circuits from the library to the ports, calculating current and voltage at each of the ports, using a cost function to calculate the cost of placement of the assigned circuits, and perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements.
Yet another aspect of the present invention provides a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design the program utilizing a library of circuits employed in designing an integrated circuit chip. The method steps comprise determining a supply current requirement and an operating voltage range for each circuit in the circuit library; calculating an admittance matrix representing the power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid; assigning regions of the power grid to each of the ports; placing a set of circuits from the circuit library in regions on the power grid; calculating a total node current at each of the ports by summing current requirements of all of the circuits located in the regions; calculating a node voltage at each of the ports by solving a pre-factorized representation of a system of linear equations corresponding to the calculated admittance matrix; imposing a penalty to each node having a node voltage outside of a predetermined range; and writing the node voltages and the penalties to a cost-based floorplanning/placement analysis tool.
Another related aspect provides a computer program product comprising a computer usable medium having computer readable program code means embodied therein for designing an integrated circuit within a power grid, the computer program product utilizing a library of circuits for use in designing an integrated circuit chip. The computer readable program code means in the computer program product comprises computer readable program code means for characterizing the circuits in the library for supply currents and voltage ranges; computer readable program code means for constructing a power grid model based on general power requirements of the integrated circuit under design; computer readable program code means for calculating an impedance matrix representing impedance between ports in the power grid model; computer readable program code means for assigning selected circuits from the library to the ports; computer readable program code means for calculating current and voltage at each of the ports; computer readable program code means for using a cost function to calculate the cost of placement of the assigned circuits; and computer readable program code means for perturbing the assignment of the circuits, if the cost of such placement does not meet design requirements.
A further related aspect of the invention provides a computer program product comprising a computer usable medium having computer readable program code means embodied therein for analyzing supply voltage drops in a power grid for distributing power to an integrated circuit chip during design, the computer program product utilizing a library of circuits employed in designing an integrated circuit chip. The computer readable program code means in the computer program product comprises computer readable program code means for determining a supply current requirement and an operating voltage range for each circuit in the circuit library; computer readable program code means for calculating an admittance matrix representing the power grid with a pre-specified array of circuit ports defined by intersection of the power grid and a modeling grid; computer readable program code means for assigning regions of the power grid to each of the ports; computer readable program code means for placing a set of circuits from the circuit library in regions on the power grid; computer readable program code means for calculating a total node current at each of the ports by summing current requirements of all of the circuits located in the regions; computer readable program code means for calculating a node voltage at each of the ports by solving a system of linear equations corresponding to the calculated admittance matrix; computer readable program code means for imposing a penalty to each node having a node voltage outside of a predetermined range; and computer readable program code means for writing the node voltages and the penalties to a cost-based floorplanning/placement analysis tool.